№ files_lp_4_process_1_39747
Analysis and comparison of conventional and BEC-based carry select adders to propose an optimized CSLA design with reduced area-delay product and energy consumption.
Year: 2026
Region / City: Kerala, India
Subject: Digital Circuit Design, VLSI, Arithmetic Units
Document Type: Research Brief / Technical Paper
Institution: Viswajyothi College of Engineering & Technology, Department of ECE
Authors: Ayana George, Cuckoo Anitha Joseph
Intended Audience: VLSI designers, DSP system engineers, researchers in digital electronics
Methodology: Logic optimization based on data dependence, use of BEC and conventional CSLA analysis
Performance Metrics: Area–Delay Product (ADP), energy consumption
Application: ASIC synthesis, square-root CSLA implementation
Technology Focus: Low-power, area-efficient VLSI design, carry select adder
Price: 8 / 10 USD
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