№ lp_1_19747
File format: docx Character count: 7740 File size: 169 KB
Academic source presenting a modified carry select adder architecture that replaces ripple carry adders with binary to excess-1 converters to analyze delay and area trade-offs in 16-bit SQRT CSLA designs.
Document type: Research paper
Field: Digital electronics
Topic: Carry select adder design
Keywords: Area-efficient, Low power, CSLA, Binary to Excess-1 Converter, Multiplexer
Adder architecture: SQRT CSLA
Technology reference: Xilinx
Focus parameters: Delay, Area, Power consumption
Circuit elements: Full Adder, Half Adder, XOR, MUX, BEC
Bit width analyzed: 16-bit
Evaluation method: Gate count and delay analysis
Price: 8 / 10 USD
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Modified Design of Area-Efficient Low Power Carry Select Adder (CSLA) Circuit
Year: 2023
Region / City: Not specified
Subject: Digital Circuit Design
Document Type: Research Paper
Organization / Institution: Not specified
Target Audience: Researchers, Engineers, Students
Period of Validity: Not specified
Approval Date: Not specified
Date of Changes: Not specified
Area-Delay Efficient Carry Select Adder Design Using Optimized Logic Formulation
Year: 2026
Region / City: Kerala, India
Subject: Digital Circuit Design, VLSI, Arithmetic Units
Document Type: Research Brief / Technical Paper
Institution: Viswajyothi College of Engineering & Technology, Department of ECE
Authors: Ayana George, Cuckoo Anitha Joseph
Intended Audience: VLSI designers, DSP system engineers, researchers in digital electronics
Methodology: Logic optimization based on data dependence, use of BEC and conventional CSLA analysis
Performance Metrics: Area–Delay Product (ADP), energy consumption
Application: ASIC synthesis, square-root CSLA implementation
Technology Focus: Low-power, area-efficient VLSI design, carry select adder
Modified Design of Area-Efficient Low Power Carry Select Adder (CSLA) Circuit
Year: 2023
Region / City: Not specified
Subject: Digital Circuit Design
Document Type: Research Paper
Organization / Institution: Not specified
Target Audience: Researchers, Engineers, Students
Period of Validity: Not specified
Approval Date: Not specified
Date of Changes: Not specified
Topics: Excess-1 Area-Efficient Adder