№ lp_1_2_26284
File format: docx Character count: 7434 File size: 257 KB
Formal guidelines for IC layout submission, including GDSII database preparation, design verification, and packaging instructions, intended for customers providing designs to SCL via ChipIN Centre.
Year: 2026
Region / City: Sector 72, S.A.S. Nagar, Punjab, India
Subject: Semiconductor Design Submission
Document Type: Technical Submission Form
Organization: ChipIN Centre, C-DAC Bangalore
Target Audience: IC designers and customers submitting layouts for fabrication
Technology Node: 180nm CMOS
Required Files: GDSII database, Process Information Sheet, DRC and Antenna reports, bonding diagram
Voltage Specifications: IO 1.8V / 3.3V / 5V, Core 1.8V / 3.3V / 5V
Metal Levels: 4M1L, 6M1L
MOSFET Types: Core 1.8V, 3.3V, 5V
Packaging Options: Chip-on-Board QFN packages, 2x2 mm² to 5x5 mm²
Price: 8 / 10 USD
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