№ files_lp_3_process_7_070737
Technical research paper presenting the design, simulation, and evaluation of an approximate multiplier with a low-complexity error compensation module for neural network and image processing applications in nanoscale digital circuits.
Authors: Kanala Vijaya Swathi; S. Lakshmi Kanth
Author Affiliation: Electronics and Communication Engineering, Annamacharya Institute of Technology and Sciences, Kadapa
Author Positions: M. Tech; Assistant Professor
Field: Digital Integrated Circuits and Approximate Computing
Keywords: Approximate computing; error-resilient applications; neural networks; image processing; ultra-efficient multiplier
Type of Document: Technical research paper
Core Contribution: Approximate multiplier with constant truncation and low-complexity error compensation module
Technology Used: 7nm tri-gate FinFET technology
Simulation Tools: HSPICE; MATLAB
Application Domains: Artificial neural networks; convolutional neural networks; image processing
Performance Metrics: Energy-delay product; Peak Signal-to-Noise Ratio (PSNR)
Structure Components: Constant-truncated region; error compensation module; exact multiplication part
Error Compensation Design: Two four-input OR gates using 20 transistors
Price: 8 / 10 USD
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